1. Field of the Invention
The present invention relates to parallel signal buses, and in particular, parallel signal buses having parallel signal lines with sufficiently close line spacings such as to introduce Miller effect capacitances between adjacent signal lines.
2. Description of the Related Art
As digital integrated circuits become more complex and operate at increasingly higher clock rates, the geometries of such devices have become significantly smaller. As a result, signal lines (e.g. in the form of metalization layer segments) are located more closely to one another, i.e. the distance between adjacent signal lines has become significantly smaller.
As such distances become smaller, the effective capacitances between such signal lines increase and, therefore, become of greater concern. Where the relative polarities of the signals on two adjacent signal lines are in opposition to one another, i.e. with signal transitions occurring in opposite directions and/or signal levels of opposite polarities or different magnitudes, the effective capacitance between such signal lines is increased due to the well known "Miller effect." In other words, as is well known in the art, the effective capacitance of the adjacent signal lines is increased by the so-called Miller effect when the magnitudes of the signals move in opposite directions. Such increases in effective capacitance cause the effective transmission rate of the signals on such lines to decrease due to the charging and discharging of the Miller effect capacitance.
One technique which may be used to reduce the Miller effect capacitance between adjacent signal lines is to simply increase the spacing between such signal lines. Another technique is to insert other lines between the active signal lines, e.g. insert power supply lines or significantly less active signal lines between those signal lines which tend to be the most active. However, both of these techniques have the disadvantage of reducing the density of the parallel signal bus. This disadvantage is increasingly troublesome as densities of parallel signal buses increase, e.g. as in the case of 16-bit and 32-bit address and/or data buses in the newer microprocessors.
Accordingly, it would be desirable to have an improve topography for a parallel signal bus which minimizes Miller effect capacitances between adjacent signal lines while simultaneously maximizing the density of the signal bus.